Comparison and combination of a hemodynamics/biomarkers-based model with simplified PESI score for prognostic stratification of acute pulmonary embolism: findings from a real world study

Background: Prognostic stratification is of utmost importance for management of acute Pulmonary Embolism (PE) in clinical practice. Many prognostic models have been proposed, but which is the best prognosticator in real life remains unclear. The aim of our study was to compare and combine the predictive values of the hemodynamics/biomarkers based prognostic model proposed by European Society of Cardiology (ESC) in 2008 and simplified PESI score (sPESI).Methods: Data records of 452 patients discharged for acute PE from Internal Medicine wards of Tuscany (Italy) were analysed. The ESC model and sPESI were retrospectively calculated and compared by using Areas under Receiver Operating Characteristics (ROC) Curves (AUCs) and finally the combination of the two models was tested in hemodinamically stable patients. All cause and PE-related in-hospital mortality and fatal or major bleedings were the analyzed endpointsResults: All cause in-hospital mortality was 25% (16.6% PE related) in high risk, 8.7% (4.7%) in intermediate risk and 3.8% (1.2%) in low risk patients according to ESC model. All cause in-hospital mortality was 10.95% (5.75% PE related) in patients with sPESI score ≥1 and 0% (0%) in sPESI score 0. Predictive performance of sPESI was not significantly different compared with 2008 ESC model both for all cause (AUC sPESI 0.711, 95% CI: 0.661-0.758 versus ESC 0.619, 95% CI: 0.567-0.670, difference between AUCs 0.0916, p=0.084) and for PE-related mortality (AUC sPESI 0.764, 95% CI: 0.717-0.808 versus ESC 0.650, 95% CI: 0.598-0.700, difference between AUCs 0.114, p=0.11). Fatal or major bleedings occurred in 4.30% of high risk, 1.60% of intermediate risk and 2.50% of low risk patients according to 2008 ESC model, whereas these occurred in 1.80% of high risk and 1.45% of low risk patients according to sPESI, respectively. Predictive performance for fatal or major bleeding between two models was not significantly different (AUC sPESI 0.658, 95% CI: 0.606-0.707 versus ESC 0.512, 95% CI: 0.459-0.565, difference between AUCs 0.145, p=0.34). In hemodynamically stable patients, the combined endpoint in-hospital PE-related mortality and/or fatal or major bleeding (adverse events) occurred in 0% of patients with low risk ESC model and sPESI score 0, whilst it occurred in 5.5% of patients with low-risk ESC model but sPESI ≥1. In intermediate risk patients according to ESC model, adverse events occurred in 3.6% of patients with sPESI score 0 and 6.65% of patients with sPESI score ≥1.Conclusions: In real world, predictive performance of sPESI and the hemodynamic/biomarkers-based ESC model as prognosticator of in-hospital mortality and bleedings is similar. Combination of sPESI 0 with low risk ESC model may identify patients with very low risk of adverse events and candidate for early hospital discharge or home treatment.

Digital phase-locked loops

Digital PLLs exploit CMOS scaling and allow accurate cancellation of fractional spurs and automatic bandwidth control. In Bang-Bang DPLLs assisted by DTC, performance is only limited by DCO and DTC resolution. Bang-Bang DPLLs assisted by DTC allow same phase-noise performance and fractional spur level as standard DPLLs at much lower power consumption

Frequency Synthesizers for 5G Applications

Fifth-generation cellular transceivers operating in the millimeter-wave band require a local oscillator in the tens of gigahertz range, with an absolute jitter below 100 fs rms. In recent years, bang-bang digital and sampling analog phase-locked loops have been demonstrated to be the practical alternatives to conventional charge-pump ones, achieving lower jitter and power consumption in nanoscale CMOS processes. The adoption of those architectures in high-performance fractional-N frequency synthesis has been possibile with the assistance of digital-to-time converters which enable the cancellation of the divider quantization noise at the input of the phase-detection block

Advanced digital phase-locked loops

▪ Analog PLLs do not scale down as process and are not amenable to noise-cancellation and other calibration algorithms ▪ Digital PLLs exploit CMOS scaling and allow for simple, accurate implementation of digiphase and two-point modulation ▪ Typically, DPLLs require TDCs with tight resolution to achieve low phase noise and fractional-spur level, which increase both power consumption and design effort ▪ DPLLs with Bang-Bang Detectors (i.e. coarse midrise TDCs) in combination with a DTC allows same phase-noise performance and fractional-spur level at much lower power consumption ▪ Fine resolution is only required to DCO and DTC, which can be both improved leveraging oversampling techniques ▪ Bang-Bang DPLLs achieve superior noise/ power trade-off over conventional DPLLs, while reducing design effort

Bang-Bang Digital PLLs

This paper compares the properties of traditional digital phase-locked loops based on multi-bit, high-resolution time-to-digital converters and those based on bang-bang phase detectors. Novel analysis is presented which show that bang-bang digital PLLs allow better phase noise and spur performance at lower power consumption, area and complexity. It will be also demonstrated that this property can be generalized to the case of PLLs based on coarse time-to-digital converters with mid- rise quantization, whose adoption speeds up lock transients. The results are assessed in a fabricated 3.6-GHz fractional-N digital phase-locked loop

Computing low-frequency noise in charge-pump phase-locked loops

An efficient simulation method to compute the low-frequency noise spectrum found at the output of charge-pump phase-locked loops is described. It is investigated how such a noise component varies as a function of the division factor

Analysis of VCO Phase Noise in Charge-Pump Phase-Locked Loops

This paper presents a phase noise analysis of charge-pump phase-locked-loops. Fundamental results from the theory of discrete-time systems are employed to derive closed-form expressions of noise transfer functions and design guidelines. The proposed expressions allows predicting the PLL in-band noise and spurs induced by VCO internal white and flicker noise sources and by external interferences coupled to VCO most sensitive nodes. To verify the correctness of the presented theoretical results, a simulation method is developed, which takes into account the time-varying nonlinear characteristics of the VCO and which is much more efficient than transistor-level noise simulations

Low Power RF Digital PLLs with Direct Carrier Modulation

The book offers unique insight into the modern world of wireless communication that included 5G generation, implementation in Internet of Things (IoT), and emerging biomedical applications. To meet different design requirements, gaining perspective on systems is important. Written by international experts in industry and academia, the intended audience is practicing engineers with some electronics background. It explains how wireless electronic circuit receive and transmit RF signals and how they play an important role in everyday life applications (mobile devices, Internet, and Bluetooth). The text further explains how modern RF wireless systems are built and used in practical systems